1. Field of the Invention
The present invention relates to a lead frame for a multiplicity of terminals, in particular of large-scale integrated semiconductor chips, arranged in a very confined space and consisting of metallic conductors, which converge from large outer spacings toward the terminals and can be connected to the terminals.
2. Discussion of Related Art
Such lead frames are used for contacting one or more large-scale integrated semiconductor chips. On their outer edge, the semiconductor chips have bonding pads which, according to the current technique, are square and have an edge length of 90 mm-120 mm and a spacing from pad to pad of at least 30 mm. The contact to the inner ends of the conductors of the lead frames is usually established by bonding wires having a diameter of 25 mm-30 mm.
The lead frames are usually produced with outer edge pieces which are parted or separated after positioning of the lead frame, so that the individual conductors of the lead frame are no longer electrically connected to one another.
Punching is the least expensive method available for the production of the lead frames. Due to the relatively high tool costs, this production method is not flexible. For relatively high numbers of terminals, the complexity of the tools increases, with the result that problems of precision multiply. Therefore, this technique is used to realize terminal numbers up to about 120.
Another known method of producing these frames is etching, by which the desired structures are etched out of a uniform metallic surface, so that the desired metallic conductors remain. The etching operation can be controlled in the usual way by photographic shadowing methods. Although this method is distinguished by low tool costs and by high flexibility, it leads to relatively high production costs because automation has not yet succeeded on an economically significant scale.
Both methods lead to a minimal terminal width and to a minimal clearance spacing between the terminals of the conductors on an order of magnitude of the material thickness, which is, for example, 150 mm. The minimal terminal width of 150 mm and the minimal spacing of likewise 150 mm leads to a terminal grid of 300 mm. On account of the limited length of the bonding wires, according to known techniques, a number of terminals of up to 160 can be achieved with a square package of 28 mm edge length (EIAJ Standard). Higher numbers of terminals can be achieved only by expensive special package configurations. These special packages, so-called arrays, have the disadvantage however that they are not suited for modern non-thruplating insertion and soldering methods.
One known method of producing very small terminal groups is based on the use of a tape carrier material (e.g. polyimide), on which a terminal grid is produced by the positive or negative method and in assembly is connected directly to the chip by soldering. The amount of solder necessary for this is applied in a number of additional processes, starting from the chip. With this "tape automated bonding" terminal widths of 50 mm with a spacing of 30 mm, that is a grid pattern of 80 mm, can be realized. However, this method is relatively expensive and inflexible. High tape material and tool costs arise, which have to be funded anew with every change in chip design. Therefore, a cost-effective production of relatively small numbers is not possible. Furthermore, these products require special insertion techniques at the customer's premises.